1. Field of the Invention
Embodiments of the present invention relate generally to image sensor circuits and, in specific embodiments, to an image sensor circuit including a pixel array, a plurality of column analog-to-digital conversion (ADC) circuits, and at least two memory blocks connected to receive digital pixel signals from corresponding column ADC circuits, where at least two of the at least two memory blocks are connected to receive digital pixel signals provided from corresponding column ADC circuits that are located to a same side of the pixel array, and where each of the at least two memory blocks includes a plurality of memory cells, one or more sense amplifiers connected to the plurality of memory cells by a readout bus, and a memory controller.
2. Related Art
Image sensors have found wide application in consumer and industrial electronics, and have enabled an explosion in the number of digital cameras and digital video devices used for work and entertainment. In many applications, and especially in industrial applications, there is a constant demand for image sensors with faster processing speed and better image quality. Thus, developers of image sensors place a high priority on identifying speed bottlenecks in image sensor designs that can limit the increasing of imager speed, and they expend great effort in attempting to eliminate such bottlenecks.
For many years, the image sensor industry was dominated by charge coupled device (CCD) technology, but there has recently been a dramatic shift toward the manufacturing of solid state imaging devices using complimentary metal oxide semiconductor (CMOS) processes in order to increase the speed and reliability of image sensors and to reduce the cost of manufacturing the image sensors. Solid state imaging devices manufactured using CMOS processes are known as CMOS image sensors. While consumer CMOS image sensors for general consumer applications typically have one or two analog-to-digital conversion (ADC) circuits on an entire image sensor chip, CMOS image sensors for more demanding applications typically utilize one ADC circuit per column of pixel circuits, or per several columns, or even two ADC circuits per column for faster processing speed and, thus, are known as high speed CMOS image sensors.
Examples of related art high speed CMOS image sensor circuits are disclosed in the following references: (i) U.S. Pat. No. 6,870,565 entitled “Semiconductor Imaging Sensor Array Devices with Dual-Port Digital Readout”, the contents of which are incorporated by reference herein and which is hereinafter referred to as reference 1; (ii) U.S. Patent Application Publication No. 2003/0043089 entitled “Doubling of Speed in CMOS Sensor with Column-Parallel ADCs”, the contents of which are incorporated by reference herein and which is hereinafter referred to as reference 2; and (iii) A. Krymski et al., “A High Speed, 500 frames/s, 1024×1024 CMOS Active Pixel Sensor”, 1999 Symposium on VLSI Circuits Digest of Technical Papers, 1999, Kyoto, Japan, pp. 137-138, the contents of which are incorporated by reference herein and which is hereinafter referred to as reference 3.
FIG. 1 illustrates a simplified architecture of a prior art high speed CMOS image sensor circuit 10. As illustrated in FIG. 1, the image sensor circuit 10 comprises a pixel array 20, a row decoder/driver 24, a column ADC block 30, an ADC controller 34, a memory 41, a memory controller 44, a readout bus 45, sense amplifiers 46, pad drivers 48, and pads 50. The pixel array 20 comprises pixel circuits 22 that are arranged in rows0 and columns. Each pixel circuit 22 comprises a light sensitive element, such as a photodiode and the like, to sample light intensity of a corresponding portion of a scene being imaged, and each pixel circuit 22 is configured to produce an analog pixel signal based on the sampled light intensity.
The row decoder/driver 24 supplies control signals to the pixel circuits 22 in the pixel array 20 to control an operation of the pixel circuits 22. Pixel circuits 22 that are in a same row of the pixel array 20 may share a common row control signal from the row decoder/driver 24. Pixel circuits 22 that are in a same column of the pixel array 20 may share a common column readout line to provide output. The row decoder/driver 24 typically controls the pixel circuits 22 to perform processing row by row.
The analog pixel signals output from the pixel array 20 are input to the column ADC block 30. The column ADC block 30 typically comprises one column ADC circuit 32 for each column of pixel circuits 22 in the pixel array 20. Each column ADC circuit 32 is configured to convert analog pixel signals received from the pixel array 20 into corresponding digital pixel signals. The ADC controller 34 controls an operation of the column ADC circuits 32, and may also control an operation of the row decoder/driver 24.
The digital pixel signals output from the column ADC block 30 are input to the memory 41. The memory 41 may comprise, for example, random access memory (RAM) cells RAM0 42 and RAM cells RAM1 43, such as in the embodiments disclosed in reference 1. Also, an example of a dual-port 2 row static RAM (SRAM) cell is illustrated in FIG. 3 of reference 3. Each RAM cell RAM0 42 stores bits from a digital pixel signal output from a corresponding column ADC circuit 32. The bits stored in each RAM cell RAM0 42 are then output and stored into a corresponding RAM cell RAM1 43. The bits stored in each RAM cell RAM1 43 are then output on readout bus 45 to sense amplifiers 46. The readout bus 45 typically comprises multiple bit lines, so that multiple bits may be transferred simultaneously. The memory controller 44 controls an operation of the RAM cells RAM0 42 and the RAM cells RAM1 43. The outputs of the sense amplifiers 46 are provided to pad drivers 48, and the pad drivers 48 drive digital signals to pads 50 that are located in various positions on the image sensor circuit 10.
In order to identify bottlenecks that limit the increasing of image sensor speed, it is helpful to first examine some constraints under which typical high speed CMOS image sensor circuits operate. A typical row processing time for a high speed CMOS image sensor circuit, such as the image sensor circuit 10 is, for example, from 500 ns to several microseconds. A typical number of columns of pixel circuits in a pixel array may be, for example, between 1,000 and 2,000 columns. Pixel control signals from a row decoder/driver to pixel circuits, and ADC control signals from an ADC controller to column ADC circuits may occupy, for example, dozens of nanoseconds because they only happen, for example, once or twice per each row processing time.
In contrast, unlike pixel circuit operations and column ADC circuit operations, memory readouts from memory cells, such as RAM cells, occur, for example, in very tight sub-clock timing. Typically, a half of a clock time is used to precharge bit lines of a readout bus, and another half of the clock time is used for reading signals from the memory cells and sensing the signals by sense amplifiers. Thus, each memory operation takes, for example, only a few nanoseconds. When clock rates for image sensor circuits, such as the image sensor circuit 10, are increased, the memory readout operations have been found to be some of the first operations to fail. As a consequence, memory readout operations have become a bottleneck for present-generation high speed CMOS image sensor circuits that can prevent further increases in image sensor speed and, hence, can prevent further increases in processing data rates.
The memory used in high speed CMOS image sensor circuits, such as the memory 41, differs from other types of memory used in applications outside of the image sensor context, because while other types of memory may typically be on the order of, for example, 1 mm long, the memory used in high speed CMOS image sensor circuits is typically on the order of, for example, 10 mm to 20 mm long. The long length of memory typically used in high speed CMOS image sensor circuits is due in part to the design of image sensors in which, for example, one or more memory cells are used for each column of pixel circuits in a pixel array, and in which the memory cells are arranged to span the length of the pixel array.
Since the number of columns of pixel circuits in a pixel array for a high speed CMOS image sensor circuit is typically between, for example, 1,000 and 2,000 columns, the length of a memory that spans the length of the pixel array is very long. Also, in order to improve image quality, it is desirable to use larger pixel circuits, which further leads to an increase in the length of the memory. A further difference between memory used in high speed CMOS image sensor circuits and memory typically used in other applications is that the memory for high speed CMOS image sensor circuits is usually configured to accept large amounts of data in parallel from a large number of column ADC circuits, while other types of memory are usually not designed to accept as much data in parallel.
In related art image sensor circuit designs, as the length of memory has increased, the length of bit lines in a readout bus, such as the readout bus 45, for reading out bits from memory have also increased correspondingly. Thus, the length of a readout bus, such as the readout bus 45, usually spans the length of a pixel array and is also typically on the order of, for example, 10 mm to 20 mm long. The extremely long lengths of readout buses from memories of related art image sensor circuits have various consequences, as will now be further explained.
As the lengths of bit lines of a readout bus increase, a resistance and a capacitance associated with the bit lines also increase. In addition, when more memory cells are added to a bit line, a capacitance associated with the bit line further increases. Thus, bit lines of a readout bus in related art image sensor circuits that have lengths, for example, on the order of 10 mm to 20 mm long, and that are connected to, for example, on the order of 1,000 to 2,000 memory cells, have high resistances and high capacitances. The high resistance of the bit lines due to the long lengths of the bit lines and the high capacitance of the bit lines due to the large number of memory cells connected to the bit lines may lead to signal degradation, and may impose physical limitations on a speed of memory readout operations.
It is instructive to consider a delay estimate for a 20 mm long readout bus in order to better understand limitations on readout operations that are imposed by a long readout bus. A typical resistance of a 20 mm long metal wire line that is 0.5 μm wide and that has resistivity of 0.1 Ohm/square is (20,000/0.5*0.1)=4 kOhm. A capacitance of the line, not including memory cell output capacitances, is approximately (0.1 fF/μm* 20,000 μm)=2 pF. Thus, the RC constant is 8 ns, which means that readout operations could not even be performed at a frequency of 100 MHz.
Moreover, when bit lines of a readout bus from memory are extremely long and, for example, span the length of a pixel array, an additional problem is created in that data signals must travel across the length of the bit lines to sense amplifiers, and then are driven by pad drivers to pads that may be located in various positions all over the image sensor circuit. Such a situation is especially problematic when signals must be driven by pad drivers to pads that are located in locations, with respect to the sense amplifiers, that are in the opposite direction of the direction in which the data signals travel across the bit lines from the memory cells to the sense amplifiers. In such a case, the pad drivers must drive the signals to pads that are located all the way back across the image sensor circuit. Driving the data signals over longer distances may result in higher power consumption to drive the signals, and may also lead to the injection of noise into a substrate that is part of the image sensor circuit.
In related art image sensor circuits, a typical skew time between signal arrival at a pad that is located closest to a pad driver and signal arrival at a pad that is located farthest away from the pad driver can be on the order of, for example, 5 ns. Such skew time may not be a very severe issue when a system clock is less than 100 MHz, but such skew time will become a severe issue as system clocks for image sensor circuits are increased to 200 MHz and higher. Also, a skew time on the order of, for example, 5 ns is large enough to require attention by systems that receive signals from pads of an image sensor circuit.
In order to increase the speed of image sensor circuits, some related art image sensor circuits allow for utilizing two analog processing and digitizing circuits, such as two column ADC blocks, each comprising a plurality of column ADC circuits, where one of the analog processing and digitizing circuits is located above a pixel array and the other analog processing and digitizing circuit is located below the pixel array in the image sensor circuit. Imaging systems with such configurations are disclosed in reference 2, although reference 2 was not the first reference to disclose imaging systems with such configurations.
FIG. 2 illustrates a simplified architecture of a prior art high speed CMOS image sensor circuit 60 having both a top column ADC block 80a above a pixel array 70 and a bottom column ADC block 80b below the pixel array 70. The image sensor circuit 60 further comprises a top memory 90a, a top readout bus 95a, top sense amplifiers 96a, and top pad drivers 98a that are located above the pixel array 70, and a bottom memory 90b, a bottom readout bus 95b, bottom sense amplifiers 96b, and bottom pad drivers 98b that are located below the pixel array 70. The image sensor circuit 60 also includes a plurality of pads 100.
The image sensor circuit 60 may be configured such that, for example, analog pixel signals output from pixel circuits in odd columns of the pixel array 70 are input to the top column ADC block 80a and analog pixel signals output from pixel circuits in even columns of the pixel array 70 are input to the bottom column ADC block 80b. In such a configuration, a number of memory cells in top memory 90a for receiving digital pixel signals from top column ADC block 80a can be reduced in half as compared to, for example, a number of RAM cells in the memory 41 of the image sensor circuit 10, because there would only need to be enough memory cells to store pixel values from the odd columns in the pixel array 70. As a consequence, a number of memory cells connected to the top readout bus 95a can also be reduced in half as compared to, for example, the number of RAM cells connected to the readout bus 45 of the image sensor circuit 10. A similar reduction in a number of memory cells connected to the bottom readout bus 95b would also result from such a configuration.
By reducing, in half, a number of memory cells connected to the top readout bus 95a as compared to, for example, the number of RAM cells connected to the readout bus 45 of the image sensor circuit 10, a capacitance associated with the top readout bus 95a is correspondingly reduced. However, in high speed CMOS image sensor circuit designs, even with the number of memory cells connected to a readout bus reduced in half, the number of memory cells connected to the readout bus may still be on the order of, for example, 500 to 1,000 memory cells, which may still result in a large amount of capacitance.
Furthermore, even in configurations with both the top memory 90a and the bottom memory 90b, there is still the problem that the top readout bus 95a and the bottom readout bus 95b span the length of the pixel array 70. Thus, a resistance associated with the top readout bus 95a and a resistance associated with the bottom readout bus 95b still remain high, as the lengths of the readout buses may still be, for example, on the order of 10 mm to 20 mm long. The high resistance and the high, though reduced, capacitance of the top readout bus 95a and the bottom readout bus 95b still impose a limit on increasing the speed of memory readout operations and, thus, the memory readout operations still remain a bottleneck.
By having the top sense amplifiers 96a and the top pad drivers 98a, signals can be driven to pads 100 located on a top portion of the image sensor circuit 60 with less power than would be required to drive signals from the bottom of the image sensor circuit 60 to the pads 100 located on the top portion of the image sensor circuit 60. However, because signals must travel across the top readout bus 95a to the top sense amplifiers 96a and then to the top pad drivers 98a, there is still a problem in that signals must travel a long way in one direction across the top readout bus 95a to the top sense amplifiers 96a and then must be driven a long distance by the top pad drivers 98a back across the image sensor circuit 60 to pads 100 located on a left portion of the image sensor circuit 60. The driving of signals across the image sensor circuit 60 results in high power consumption, and may result in the injection of digital noise into a substrate that is part of the image sensor circuit 60. Similar problems exist in driving signals by the bottom pad drivers 98b to pads 100 located on the left portion of the image sensor circuit 60.
Also, in order to increase the speed of image sensor circuits, some related art image sensor circuits use multiple buses to perform readout of data from memory. For example, some related art image sensor circuits include 8 buses, where memory cells 1, 9, 17, . . . in a row are connected to a first bus, memory cells 2, 10, 18, . . . in the row are connected to a second bus, and so on for each bus, where the memory cells in the row that are connected to a same bus are separated by 8 memory cells. The memory cells 1-8 can then be selected at once for memory readout. Such a configuration reduces a number of memory cells connected to a single bus by, for instance, 8 times and, as a result, reduces a capacitance associated with each bus as compared to a single bus configuration. However, even in such a configuration, each readout bus must still have a length that spans a length of the pixel array and is on the order of, for example, 10 mm to 20 mm long. Thus, such a configuration still has the problems that are associated with long readout buses as discussed above.
While memory readout operations are one bottleneck that limits the increasing of imager speed, another bottleneck is the amount of time needed to send control signals from an ADC controller to all column ADC circuits in a column ADC block. For example, in the image sensor circuit 10, the ADC controller 34 must supply control signals to the column ADC circuits 32 of the column ADC block 30. Since the ADC controller 34 is located to the left of the column ADC block 30, control lines from the ADC controller 34 to column ADC circuits 32 located near the right side of the column ADC block 30 are very long because the column ADC block 30 is typically around the same length as the pixel array 20, which may be, for example, on the order of 10 mm to 20 mm long. The time needed for control signals to reach all column ADC circuits from an ADC controller further imposes a limit on an increasing of imager speed.
In the area of CCD technology, there has been known an architectural method known as “paneling” for increasing the data rate of image sensors based on CCD technology. With paneling, a CCD image sensor is formed by several independent CCD panels, each having a separate pixel array and separate amplifiers, and each performing a separate readout. An example of paneling in a CCD image sensor is disclosed in U.S. Pat. No. 5,757,520 entitled “Color Linear Image Sensor and an Image Processing System”, where FIG. 8 of U.S. Pat. No. 5,757,520 illustrates two CCD sensor chips packed into a single sensor package.
However, there has been a problem with paneling in CCD technology in that a discontinuity between panels of pixels may result in an image non-uniformity at the boundaries of the panels. Such image non-uniformities may be unacceptable to end users. Also, a difference between the amplifiers serving separate panels and a difference in local parasitic effects between panels may result in response non-uniformities between the panels. The problems arise due in part to the splitting of pixel arrays into separate panels, where each pixel array outputs analog signals.
In light of the above mentioned problems, there is a need for high speed CMOS image sensor circuits that allow for reducing an amount of time required for memory readout operations. There is also a need for high speed CMOS image sensor circuits that allow for reducing the distance that signals must be driven to reach output pads. In addition, there is a need for high speed CMOS image sensor circuits that allow for reducing an amount of time required to send control signals from an ADC controller to column ADC circuits in a column ADC block. It is also desired that such high speed CMOS image sensor circuits be easy to design and implement, and that they preserve the uniformity of output images.